1. Technical Field
The present invention relates to a clock signal initialization circuit and its method, and in particular to a clock signal initialization circuit that initializes a clock signal generated by a PLL (Phase Locked Loop) circuit and its method.
2. Background Art
In recent years, semiconductor integrated circuits have increasingly become larger in scale and their operating speeds have increasingly become higher. As a result, it is a significant challenge to reduce their power consumption. The operating frequency of such semiconductor integrated circuits depends on the frequency of a clock signal generated by a PLL circuit, and it is necessary to control the operating frequency of the semiconductor integrated circuit so that the operating frequency does not exceed the maximum permissible frequency determined based on the power consumption of the semiconductor integrated circuit even when the semiconductor integrated circuit is in a transient state such as at the start-up of this PLL circuit.
Japanese Patent No. 3119628 discloses a technique for reducing the power consumption of a clock synchronization type semiconductor integrated circuit at the power-on. An example of a technique disclosed in Japanese Patent No. 3119628 is briefly explained hereinafter with reference to FIG. 5. A high-speed clock oscillator 11 for a normal operation and a low-speed clock oscillator 12 for reducing power consumption are provided. Upon power-on, a clock signal SDRAM (Synchronous Dynamic Random Access Memory) clock 16 to be supplied to an SDRAM 14, which is an example of the semiconductor integrated circuit, is switched to the low-speed clock side for a predetermined time period in a clock switching circuit 13 by using a power-on reset signal 18 that is generated by a reset IC (circuit) 15 and output through an inverting circuit 17.
Further, an example of another technique using a PLL circuit disclosed in Japanese Patent No. 3119628 is briefly explained hereinafter with reference to FIG. 6. Note that in FIG. 6, the equivalent components/parts to those in FIG. 5 are denoted by the same symbols. In the example shown in FIG. 6, a semiconductor integrated circuit has a mode in which a PLL through signal 20 (which is also a power-on reset signal) that is used to make a low-speed clock supplied from a low-speed clock oscillator 12 pass through (bypass) a PLL circuit 19 when the low-speed clock is selected by a clock switching circuit 13 upon the power-on is enabled and the low-speed clock thereby passes through (bypasses) the PLL circuit 19.
Further, Japanese Unexamined Patent Application Publication No. 2005-339310 proposes, as a semiconductor integrated circuit capable of preventing an abrupt current consumption change from the viewpoint of the synchronous clock, a circuit that changes the frequency of a clock signal from a low frequency to a high frequency in a stepwise manner when the semiconductor integrated circuit returns from a power-on reset period or a standby state to a normal state.
That is, when the semiconductor integrated circuit returns from a power-on reset period or a standby state, the circuit changes the frequency of a clock signal from a low frequency to a high frequency in a stepwise manner by switching and controlling the output state of a frequency division circuit by using a select circuit. In doing so, the output-stabilized state of a PLL circuit is notified to an output control circuit by using a control signal. Further, until this state is notified, the output control circuit controls a clock signal for an output gate provided at the output of the output control circuit by using an output disable signal and thereby prevents any wasteful current from flowing in the transient stage (see paragraph [0035] of Japanese Unexamined Patent Application Publication No. 2005-339310).
In the technique disclosed in Japanese Patent No. 3119628, there is the following problem in the initialization process of a semiconductor integrated circuit that operates in synchronization with a clock signal generated by a PLL circuit. That is, the switching between the high-speed clock oscillator for a normal operation and the low-speed clock oscillator for reducing power consumption is performed by using the power-on reset signal.
Therefore, the frequency of a clock signal that drives the clock synchronization type semiconductor integrated circuit is set to a lower value than that for the normal operation for a predetermined time period after the power-on, and this setting is made irrelevantly to the operating state of the PLL circuit. Therefore, there is a possibility that if the PLL circuit is still in the start-up transient state and in the unlocked state at the time of switching and its clock signal is oscillating at a frequency higher than the assumed frequency range, the power consumption could increase beyond the assumed power consumption range.
The problem in the technique disclosed in Japanese Unexamined Patent Application Publication No. 2005-339310 is that the clock signal cannot be stopped when the clock signal is required to fix the reset state during the power-on reset period. On the other hand, when the clock signal is not stopped, Japanese Unexamined Patent Application Publication No. 2005-339310 does not mention any specific method for determining the frequency division ratio of the frequency division circuit that divides the frequency of the clock signal. Therefore, there is another problem that there is a possibility that the oscillating frequency in the unlocked and transient state upon the start-up of the PLL circuit could exceed the assumed frequency range even after the frequency is divided.